1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing the same. Specifically, the invention relates to a semiconductor device including a heat sink coupled to a semiconductor chip via a highly thermally conductive material and a method of manufacturing the same.
2. Description of the Related Art
In recent years, electronic devices, such as computers, cellular phones, and PDAs (Personal Digital Assistance) have been small-sized, sophisticated, and made to operate at a high speed. Accordingly, small, fast, high-density semiconductor devices with semiconductor chips, such as ICs (integrated circuits) and LSIs (large-scale integrated circuits), for such electronic devices are further desired. Consequently, such small, fast, high-density semiconductor devices may consume more power, causing the heat value per unit volume to increase.
As a structure for mounting a semiconductor chip, there is a structure for flip-chip bonding a semiconductor chip to a substrate using solder bumps with the side on which electrodes are formed facing down. However, such a flip-chip bonded semiconductor device may also cause a problem in that stress is generated in the area coupled with the solder bumps due to the heat depending on the difference in coefficients of thermal expansion between the semiconductor chip and the substrate, reducing the connection reliability.
A technique according to Japanese Unexamined Patent Application Publication No. 11-354677 is, therefore, proposed in order to address problems, such as stress generated in the connected area when a semiconductor chip and a substrate having different thermal expansion coefficients are connected with connecting members such as solder bumps.
Specifically, in Japanese Unexamined Patent Application Publication No. 11-354677, a technique is proposed, in which a member (lid) having a value of a thermal expansion coefficient identical or approximately identical to that of the substrate is used for packaging. Consequently, such a technique suppresses stress generated in a coupling member that individually couples a plurality of pads provided on the substrate to a plurality of input terminals provided on the semiconductor chip.
The technique according to Japanese Unexamined Patent Application Publication No. 11-354677 is described below with reference to the drawings.
FIG. 15 is a diagrammatic view for illustrating a semiconductor device in related art, and a semiconductor device 101 shown in the drawing includes a wiring substrate 102, a semiconductor chip 103, and a lid 104 provided on the upper side of the semiconductor chip 103.
The wiring substrate 102 has a plurality of pads 105, and the pads 105 are connected to wiring disposed on the surface or inside the layer of the wiring substrate 102.
The semiconductor chip 103 is flip-chip bonded to the wiring substrate 102 with the surface facing down. In addition, a plurality of input and output terminals 106 are provided on the lower side (surface) of the semiconductor chip 103, and the input and output terminals 106 are aligned in a matrix and disposed at positions corresponding to the plurality of pads 105 on the wiring substrate 102. Each of the plurality of input and output terminals 106 is connected to the corresponding one of the plurality of the pads 105 by solders 107.
The lid 104 is provided with a recess and has the cross-section in the recessed form. The bottom side of the recess is bonded to the upper side of the semiconductor chip 103 with a highly thermally conductive adhesive material 108. The end edge of the lid 104 is bonded to the upper side of the wiring substrate 102 with an adhesive material 109. The semiconductor chip 103 is thus in the state of fully sealed by the lid 104, the adhesive material 109, and the wiring substrate 102.
The lid 104 is made of copper or brass. The thermal expansion coefficient of copper is 16.5×10−6/° C. and the thermal expansion coefficient of brass is 17.3×10−6/° C., which are the values approximately identical to the thermal expansion coefficient of the wiring substrate 102 (15 to 20×10−6/° C.).
In this way, the technique according to Japanese Unexamined Patent Application Publication No. 11-354677 suppresses stress applied to the solders 107 by making the lid 104 with a material having a thermal expansion coefficient identical or approximately identical to that of the wiring substrate 102.
When a semiconductor chip is flip-chip bonded to a wiring substrate, an underfill material is typically used for reinforcement in order to protect electrically connected areas between the wiring substrate and the semiconductor chip. Specifically, after a gap between the wiring substrate and the semiconductor chip is filled with a liquid underfill material containing an epoxy resin and the like as a major component, heat is applied to the underfill material for curing, and thereby the electrically connected areas between the wiring substrate and the semiconductor chip can be reinforced.
However, warpage occurs in the wiring substrate due to the influence of the heat for curing the underfill material, so that the gaps between the wiring substrate and the lid vary from package to package and there is a variation even within a package. Accordingly, in order to securely fix the lid to the wiring substrate, the amount of the adhesive material to be applied between the wiring substrate and the lid may be increased, and as a result, there has been a problem of leakage of the adhesive material.
In other words, in a case in which the gaps between the wiring substrate and the lid vary, when the adhesive material is applied with an assumption that the gap between the wiring substrate and the lid is small, the amount of the adhesive material may be insufficient and there is a possibility that the lid is fixed insufficiently. Accordingly, a large amount of the adhesive material has to be applied with an assumption that the gap between the wiring substrate and the lid is large, which leads to leakage of the adhesive material, resulting in problems, such as causing defects in packages and braking air vents.
Therefore, in order to prevent the adhesive material from leaking out of the package outline while securing a sufficient connection between the lid and the wiring substrate, a recess for bonding 120 slightly smaller than the size of the lid is formed in a lid as shown in FIG. 16.
In other words, the problems such as causing defects in packages and braking air vents are addressed by holding the leaked adhesive material in the recess for bonding 120, even when the adhesive material leaks out with a large amount of the adhesive material being applied with an assumption that the gap between the wiring substrate and the lid is large. The symbol A in FIG. 16 indicates the leaked adhesive material.